1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices. More particularly, the present invention relates to LCD devices having polycrystalline thin film transistors (TFTs) and methods of fabricating the same.
2. Discussion of the Related Art
Due to their high portability and low power consumption, flat panel display (FPD) devices have been the subject of recent research. Among the various types of FPD devices, LCD devices are widely used as monitors for notebook and desktop computers because of their ability to display high resolution images, colors, and moving images.
Generally, an LCD device includes two substrates separated from each other by a liquid crystal layer, wherein each substrate supports electrodes, and wherein electrodes supports electrodes that disposed such that respective electrodes of the two substrates face into each other. When a voltage is applied to the electrodes, an electric field is generated which affects the orientation of liquid crystal molecules within the liquid crystal layer. Consequently, light transmittance characteristics of the liquid crystal layer become modulated and images are displayed by the LCD device.
Active matrix-type LCD devices include a plurality of pixel regions arranged in a matrix pattern, wherein each pixel region includes a switching element such as a TFT. Due to their composition, active-matrix LCDs are able to display high quality moving images. TFTs of such LCD devices may be formed using polycrystalline silicon (i.e., polycrystalline type TFTs) or amorphous silicon (i.e., a-Si type TFTs). Driving circuits of LCD devices incorporating polycrystalline silicon type TFTs can beneficially be formed on the same substrate as TFTs within the pixel regions and the necessity of additional processes to connect the TFTs of the pixel regions with driving circuits may be eliminated. Because polycrystalline silicon has a field effect mobility greater than that of amorphous silicon, LCD devices incorporating polycrystalline type TFTs beneficially include driving integrated circuits (ICs) and array elements (i.e., TFTs within the pixel regions) formed on the same substrate. Accordingly, the material cost for the driving ICs is reduced and the process of fabricating the LCD devices is simplified. Further, because polycrystalline silicon has a field effect mobility than a-Si, LCD devices incorporating polycrystalline silicon type TFTs have faster response times and increased resistance to the deleterious effects of heat and light.
Polycrystalline silicon can be formed by crystallizing amorphous silicon. One related art process of crystallizing amorphous silicon employs a laser annealing method, whereby a laser beam is irradiated onto the surface of an amorphous silicon film to generate temperatures of about 1400° C. At such temperatures, however, the irradiated surface of the amorphous silicon film oxidizes. Accordingly, where the laser annealing occurs in an oxygen containing environment while a laser beam is repeatedly irradiated onto the surface of the amorphous silicon film, silicon oxide (SiO2) is formed on the irradiated surface. Therefore, the laser annealing process must be performed in a vacuum of about 10−7 to 10−6 Torr to prevent formation of the silicon oxide. While, the above-described laser annealing method produces polycrystalline silicon having very large grains, the area of the grain boundaries in the polycrystalline produced is also very large, which can contribute to the unacceptable generation of leakage currents.
In order to solve problems of the above-described laser annealing method, a sequential lateral solidification (SLS) method has been provided. The SLS method leverages the natural tendency of silicon grains to grow along a direction perpendicular to a phase boundary between of a liquid phase region and a solid phase region. Accordingly, the lateral growth of silicon grains may be controlled by adjusting an energy density, an irradiation range, and motion of a laser beam. (Robert S. Sposilli, M. A. Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956˜057, 1997) By controlling growth of the silicon grains as described above, the area of the grain boundaries may be minimized, thereby minimizing the generation of leakage current.
FIG. 1 illustrates a schematic view of a related art LCD device including a driving circuit and array elements arranged on the same substrate.
Referring to FIG. 1, a substrate 2 supports a centrally arranged pixel area 4 and a driving circuit area 3 arranged at a periphery of the pixel area 4. The driving circuit area 3 includes a gate driving circuit 3a and a data driving circuit 3b arranged at left and top portions of the pixel area 4, respectively. The pixel area 4 includes a plurality of gate lines 6 connected to the gate driving circuit 3a, a plurality of data lines 8 connected to the data driving circuit 3b and crossing the plurality of gate lines 6 to define pixel regions, a plurality of pixel electrodes 10 arranged within the plurality of pixel regions, and a plurality of TFTs “T” to the pixel electrodes 10.
The gate and data driving circuits 3a and 3b, respectively, are connected to an input terminal of an external signal, adjust the external signal, and supply the adjusted signals to the pixel electrodes 10. Specifically, the gate driving circuit 3a supplies scan signals to the pixel electrodes 10 via the gate lines 6 and the data driving circuit 3b supplies data signals to the pixel electrodes 10 via the data lines 8. The gate and data driving circuits 3a and 3b consist of a plurality of polycrystalline silicon type TFTs formed by crystallizing amorphous silicon via an SLS method.
FIG. 2A illustrates a schematic view of a related art mask used in a sequential lateral solidification method. FIG. 2B illustrates a schematic view of a silicon layer crystallized using the related art mask of FIG. 2A.
Referring to FIG. 2A, the related art mask 14 includes a slit pattern 12 several micrometers (e.g., about 2 μm to about 3 μm) wide. Accordingly, a laser beam several micrometers wide may be irradiated onto the surface of a silicon layer. While not shown in FIG. 2A, the related art mask 14 may include a plurality of slit patterns 12 spaced apart from each other by several micrometers.
Referring to FIG. 2B, a laser beam (not shown) is irradiated through the slit pattern 12 in mask 14 shown in FIG. 2A and onto the surface of an amorphous silicon layer 20. Region 22 illustrates the irradiated portion of the amorphous silicon layer 20. Upon being irradiated by the laser beam, region 22 the amorphous silicon layer 20 becomes completely molten and subsequently cools to form grains 24a and 24b. Accordingly, region 22 may be referred to as a unit crystallization area. During cooling of the molten amorphous silicon material, grains 24a and 24b grow laterally away from opposing ends of the unit crystallization area 22 toward a central portion of the unit crystallization area 22. Accordingly, a grain boundary 28b is formed where the grains 24a and 24b meet in the central portion of the unit crystallization area 22. An entirety of the amorphous silicon layer 20 may be fully crystallized by repeating the irradiation process described above onto other surfaces of the amorphous silicon layer 20.
FIG. 3 illustrates a schematic view of a polycrystalline silicon layer formed in accordance with a related art sequential lateral solidification method.
Referring to FIG. 3, a polycrystalline silicon layer formed by the aforementioned related art SLS method generally includes a plurality of unit crystallization areas 30 and first and second overlapping areas 40 and 50 (i.e., areas of the silicon layer that were repeatedly irradiated with the laser beam). The first overlapping area 40 is arranged between transversally adjacent unit crystallization areas 30 and the second overlapping area 50 is arranged between longitudinally adjacent unit crystallization areas 30. Because the first and second overlapping areas 40 and 50 are irradiated several times, the crystallinity of the polycrystalline silicon material found within the first and second overlapping areas 40 and 50 is non-uniform. When TFTs of the pixel regions include polycrystalline silicon having non-uniform crystallinity, the display quality of the LCD device is degraded.
FIGS. 4A to 4D illustrate schematic cross-sectional views of a related art process of fabricating a polycrystalline silicon type TFT.
Referring to FIG. 4A, a buffer layer 62 is formed on a substrate 60 and a polycrystalline silicon layer 64 is formed on the buffer layer 62. The polycrystalline silicon layer is obtained by an crystallizing amorphous silicon layer as described above.
Referring to FIG. 4B, a gate insulating layer 66 and a gate electrode 68 are sequentially formed on the polycrystalline silicon layer 64.
Referring to FIG. 4C, the polycrystalline silicon layer 64 is doped with impurities using the gate electrode 68 as a doping mask. Accordingly, the polycrystalline silicon layer 64 includes a channel region “i” defined by source and drain regions “ii” and “iii” formed at opposing sides thereof, wherein the portion of the polycrystalline silicon layer 64 in the channel region “i” does not include impurities, and wherein the portions of the polycrystalline silicon layer 64 in the source and drain regions “ii” and “iii” include impurities.
Referring to FIG. 4D, portions of the polycrystalline silicon layer 64 in the source and drain regions “ii” and “iii” are “activated” in a heat treatment. Specifically, impurities introduced into the polycrystalline silicon layer 64 during the doping process outlined in FIG. 4C cause portions of the polycrystalline silicon layer 64 in the source and drain regions “ii” and “iii” become amorphized. Consequently, the impurities cannot adequately function as charge carriers for the subsequently formed TFT. Accordingly, the “activating” heat treatment consisting of a laser annealing method is performed to re-crystallize the amorphized portions of the polycrystalline silicon layer 64 and allow the impurities to adequately function as charge carriers.
Referring back to FIG. 4C, the source and drain regions “ii” and “iii” are formed in a self-aligning process (i.e., the structure of the device itself—the gate electrode 68—is used as a dopant mask, obviating the need for additional dopant masks). Thus, the TFT fabricated using the doping process outlined in FIG. 4C is referred to as a self-aligned TFT.
While obviating the need for additional dopant masks, the related art TFTs fabrication method shown in FIGS. 2A-2D, however, undesirably requires the activation step that re-crystallizes amorphized, previously crystallized silicon material. Moreover, because the gate electrode 68 is used as the doping mask and the polycrystalline silicon layer 64 is activated with the gate electrode 68 formed thereon, the polycrystalline silicon layer 64 contains a junction region “iv” aligned with edges of the gate electrode 68 that has a poor crystallinity which can promote undesirable leakage current and degrade the electrical characteristics of the TFT.